Uri Shaked
Implements the logic of a single game of life cell
Luca Horn
Replica of the long abandoned and forgotten S2650 8-bit architecture. Only implements a subset...
Cra2yPierr0t | https://cpu-dev.github.io
PicoRV & Jacaranda-8 - It's a hobby heterogeneous processor!
Paweł Sitarz
Project instantiates HyperRAM controller for external memory chip (8MB version) connected to...
Nishad Potdar
This is an implementation of BCD to Seven Segment Decoder. The module takes 4 bit BCD input and...
Abdul Moiz Sheikh
The project aims to deliver a dual mode hashing accelerator which is capable of high speed...
Myrtle Shah
FABulous eFPGA fabric generated and taped out on the new gf180 process
Ruige Lee
This is the simplest version of Rift2Core. Rift2300 has no L2 cache, no L1 ICache, no L2 TLB, no...
FPGA based on FABulous but using an experimental combined custom bitcell+tgate config routing element
Serial peripheral interface (SPI) is one of the most widely used interfaces between...
Thorsten Knoll
The historic arithmetic-logic-unit (ALU) 74181 from the 70's. Pure combinatorial with 4-bit...
Alexander Shabarshin
This is a test circuit for 3-rail async ternary selector that connects one of the 3 ternary...
Staf Verhaegen
Implementation of ChipFlow example SoC with 3.3V version of the c4m-flexcell standard cells.
Xuanjia Bi | https://engineering.virginia.edu/high-performance-low-power
This is state machine that monitors water and temperature change in a closed feedback loop.
Mehdi Saligane
TBD
Uri Shaked | https://wokwi.com
Barebore transistors
SPELL is a minimal, stack-based programming language created for The Skull CTF.
susana ortega cisneros | https://unidad.gdl.cinvestav.mx/
Another test of gf180 with a synchronous modulator for another doctoral student in electronic...
reduced size version of the one-hot mux fabric
Opensource FoodRev Projects
Wavelet Transform with pre-filters
Asma Mohsin | https://tinytapeout.com
Convolution Neural Network co processor is added with RISCV to enhance the performance of...
Greg Davill
An award winning serial RISCV SoC from Olof Kindgren. This project incorporates 3 separate...
Ryan Matthew Price | https://www.utep.edu/engineering/ece/
Experimental Digital Process Blocks for Incomplete PDK
Emilio Baungarte | https://unidad.gdl.cinvestav.mx/
Testing an ALU using gf180 technology, to support a recently submitted journal article titled,...
Rolf Widenfelt
16x4 bit dual port register file, with dual read ports and a single write port - perfect for the...
luis adolfo luna | https://unidad.gdl.cinvestav.mx/
Test of gf180 with an asynchronous modulator, which is part of a PhD project at Cinvestav in...
Vrushabh Damle
This is an implementation of a 4-bit carry look-ahead adder which is a fast adder. It has two...
Govindu Sathvik Reddy
Developed a 16bit processor having its own Reduced Instruction Set with least possible number of...
Philipp Guhring | https://libresilicon.com/
Automatically generated Test Structures with the DanubeRiver Tool, to test the Global Foundries...
Aloke Das
This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bits wide....
Subash Polisetty
8-bit Universal Shift register that performs various operations based on a control input
Janani Aravind
ALU-Radiation Hardened By Design
Anish Singhani
A group submission including several small designs contributed by students at Carnegie Mellon in...
Matt Venn | https://zerotoasiccourse.com
My VGA clock rehardened for GF180
Dinesh Annayya
Riscduino Peripheral Extension Chip Set-1
This is a second test-design which provides several automatically generated standard cells...
Komal Gupta | https://www.iiti.ac.in/
2x2 Matrix multiplication of inputs of 8 bits each . Used for solving AC network equations in...
Brown Deer Technology | www.browndeertechnology.com
This is a processor design that evolved from a tiny tapeout submission. The core implements a...
James Tandon | https://www.csueastbay.edu
A basic pulse with modulation core with 8 PWMs controled by a wishbone bus slave interface. The...
Jorge Angarita Perez
A custom 5-bit multiplier
Russell Friesenhahn
Matt Venn's famous VGA clock with SPI control
This is a test-design which provides several automatically generated standard cells directly...
Tamas Hubai
Implement any combinatorial logic on 4 inputs by wiring up the pins the right way
Third iteration of open-source cryptography core implementation
Nicolas Orcasitas Garcia
Small digital circuit that calculates the sum of the multiples of 3 and 5 until a previously...
ASIC implementation of the iconic Beep Boop traffic light at Carnegie Mellon University...
Aedan Cullen
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Wenting Zhang
VerilogBoy Game Console SoC
RAHUL SREEKUMAR | https://engineering.virginia.edu/high-performance-low-power
The Rivest Cypher 4 is a stream cipher algorithm developed in the 1980s, remarkable for its fast...
Miles Segal
calculates state of cell based on state of neighbors
Ivan Rodriguez Ferrandez
The main goal of this project is to assess the reliability of the Global foundries 180nm...
There is a LFSR in it.
Julien OURY
Christmas tree controller (MPW5 ReRun)
Egor Lukyanchenko
Uranus eFPGA with nonvolatile config in eFuse array.
Vijayan Krishnan | https://www.chipwaretechnologies.com/
The Advanced Encryption Standard (AES) is a symmetric block cipher chosen by the U.S. government...
Maximilien Dagois
LFSR 8-bit using DSLX
bitluni | https://bitluni.net
Pesistence of vision display character ROM and grphics driver
Vijayan Krishnan | https://www.chipwaretechnologies.com
Digital to Analog Converter (DAC) is a device that transforms digital data into an analog signal...
Matt Venn
A demo for GF180
Nestor Matajira
Returns the nth number of the fibonacci sequence
Laura Patricia Garcia Tiscareno | https://unidad.gdl.cinvestav.mx/
This is a clock divider of 2, 4, 8, 16, 32, 64, 128, 256, 512, and 1024. This project will help...
Uriel Jaramillo Toral | https://unidad.gdl.cinvestav.mx/
This is a small project that provides the necessary output pins to display the word posoco2000...
This project is testing Wokwi to GF180 path and having a number of basic triggers to try, namely...
Joshua Stevens
Half H Bridge driver controller for micro motors
Anton Blanchard
Microwatt is a 64 bit OpenPOWER core written in VHDL. This version doesn't include an FPU due to...
Dr Mehdi Khan
vga
Jan Patrovsky
General purpose hash accelerator/cracker.
Johan Euphrosine (proppy)
Test project based on https://github.com/proppy/tiny_user_project
Debayan Mazumdar
This project implements a RAM of 16 bytes using structural modelling. The components used are a...
Implementation of ChipFlow example SoC with 5V version of the c4m-flexcell standard cells.
Maximo Balestrini
Hardware implementation of the Hack Computer from the Nand to Tetris courses
TinyTapeout design implementing a Population count using XLS: Accelerated HW Synthesis toolkit.
Muhammed Ceylan Morgul
An 8-bit multiplier, with main logic mostly combinational, holds input with registers.
Wokwi driven testdesign which implements a 8x8 bit serial programmable, addressable and playable memory.
Dr Mehdi Khan | www.upplysningavancez.com
Project of Artificial heart
Matt Venn | https://tinytapeout.com
Displays 'TinyTapeout' on the 7 segment display
Harry Snell
Basic digital designs (PDM core and a dice using LFSR)
Leo Moser
A generic waveform generator divided into stimulus and driver units that can be arbitrarily...
Jerry Yin | https://engineering.virginia.edu/high-performance-low-power
This is a design with five 4-bit up-counters for monitoring the voltage changes
Vision-VLSI Industry PVT. LTD.
16-bit koggestone adder Verilog HDL implementation.
Filippo Carastro
A starting project for a future solar inverter processor.
Daniel Barrios
Small Test Digital Project that calculates the orbit of a N number using the Collatz Conjecture
Sai Charan
Quad 3-input Fredkin gate IC which can be programmed into the 3 primitive logic gates - AND, OR and...
This is a counter with clock, reset, io_out.
