Here are
12 public repositories
matching this topic...
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universitat Dresden, Germany
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Updated
Nov 29, 2020
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VHDL
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
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Updated
May 29, 2024
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VHDL
Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
Multi-Processor System on Chip verified with UVM/OSVVM/FV
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Updated
Jun 7, 2024
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SystemVerilog
Library of reusable VHDL components
System on Chip verified with UVM/OSVVM/FV
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Updated
Jun 7, 2024
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SystemVerilog
Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.
Processing Unit verified with UVM/OSVVM/FV
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Updated
Jun 7, 2024
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SystemVerilog
Design & Verification of IP Cores and ICs, Artificial Intelligence
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Updated
Feb 24, 2024
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VHDL
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Updated
Jun 26, 2023
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VHDL
Open Source VHDL Verification Methodology
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Updated
Jun 7, 2024
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SystemVerilog
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