Here are
68 public repositories
matching this topic...
simavr is a lean, mean and hackable AVR simulator for linux & OSX
VCD file (Value Change Dump) command line viewer
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
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Oct 27, 2022
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Python
Facilitates building open source tools for working with hardware description languages (HDLs)
Scripts to build and use docker images including GHDL
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Jun 6, 2024
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Shell
Quickstart guide on Icarus Verilog.
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Jun 18, 2020
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Verilog
A place to keep my synthesizable verilog examples.
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Jul 10, 2023
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Verilog
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Nov 29, 2017
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Java
Easy and fast VHDL simulation tool, integrating GHDL and GTKWave
Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
Python classes to create agnostic wave files for HDL simulator viewer
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Mar 8, 2020
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Python
iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.
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Mar 4, 2023
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TypeScript
Utilities for working with Verilog within Bazel.
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Oct 25, 2020
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Python
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
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Mar 22, 2024
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Verilog
Containerized open and free development tools for Dynamic Binary Hardware Injection (DBHI)
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Jan 24, 2023
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Dockerfile
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
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Sep 27, 2022
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Verilog
Example how to use the Fast Signal Trace (FST) format and library
Template for creating VHDL project using docker
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Mar 20, 2020
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VHDL
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