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13 public repositories
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Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
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Jun 15, 2024
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VHDL
Interfacing VHDL and foreign languages with VUnit
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Feb 20, 2020
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Python
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
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Feb 26, 2024
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Dart
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Aug 23, 2022
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Rust
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
GTKWave Decoders for RISCV
Enables the co-simulation between PSS/E and Matlab/Simulink
CoSys MAP 2020: Integrating Physical and Virtual Objects in a Simulation Environment
Set of utilities to export/import FMUs out of existing C++ code
CoSimo dreams of becoming a co-simulation compositor for generic simulations.
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Mar 2, 2022
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Python
Integration test between Verilog and C++ using VPI
coherence integrates evolutionary computation and co-simulation for the systematic design of protocols for cell culture and biofabrication.
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May 16, 2022
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Python
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