Memoria volatilis dynamica
vel
vehemens
[2]
est genus
memoriae volatilis
quae quodque
datorum
bit
in
condensatro
separato intra
circuitum integratum
reponit. Condensatrum
electrice
aut onerari aut non onerari potest; qui bini status binas aestimationes unius bit repraesentare habentur, usitate
0
et
1
appellatas. Quia
transistra
quae non conducunt parvam summam paulatim amittunt, condensatra
energiam
lente liberare solent, et data denique evanescunt nisi onus condensatri interdum
redintegratur
. Quia redintegratio necessaria est, haec
memoria
est dynamica, contra
memoriam volatilem staticam
et alia statica memoriae genera. Memoria volatilis dynamica,
memoriae fulgureae
dissimile, est
volatilis
(contra
memoriam non volatilem
), quia data cito amittit cum
electricitas
tollatur; memoria autem volatilis dynamica certam
datorum remanentiam
monstrat.
Memoria volatilis dynamica late in
electronica
digitali adhiberi solet, ubi memoriae vilis capacissimaeque opus est. Una e maximis memoriae volatilis dynamicae adhibitionibus in
computatris
hodiernis est
memoria principalis
(sermone humili
RAM
appellata).
Nexus interni
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2008
.
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2008
.
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ISBN 0470184752
.
ISBN 9780470184752
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- Siddiqi, Muzaffer A.
2013
.
Dynamic RAM : technology advancements.
Boca Raton Floridae: Taylor & Francis.
ISBN 9781439893739
.
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DRAM density and speed trends.
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Benefits of Chipkill-Correct ECC for PC Server Main Memory.
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What every programmer should know about memory.
- Johnston, A.
2000
.
Scaling and Technology Issues for Soft Error Rates
Stanford University.
- Mandelman, J. A., R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li, et C. J. Radens.
2002
.
Challenges and future directions for the scaling of dynamic random-access memory (DRAM).
IBM.
- Patterson, David.
Multi-port Cache DRAM?
MP-RAM.
- Wang, David Tawei.
2005
. Modern DRAM Memory Systems: Performance Analysis and a High Performance, Power-Constrained DRAM-Scheduling Algorithm. Diss. Ph.D. Collegium Universitatis Terrae Mariae.
PDF.