Description
The QSPI flash controller is automatically enabled on power-up, and will
immediately initiate a read sequence in single-bit mode
with pin
flash_io0
acting as
SDI
(data from flash to CPU)
and pin
flash_io1
acting as
SDO
(data from CPU to flash).
Protocol is according to, e.g.,
Cypress S25FL256L
.
The initial SPI instruction sequence is
as follows:
.
Table 12
Initial SPI instruction sequence
0xFF
|
Mode bit reset
|
0xAB
|
Release from deep power-down
|
0x03
|
Read w/3 byte address
|
0x00
|
Program start address (
0x10000000
) (3 bytes) (upper byte is ignored)
|
0x00
|
|
0x00
|
|
The QSPI flash continues to read bytes, either sequentially on the same command,
or issuing a new read command to read from a new address.
QSPI access modes
Table 14
reg_spictrl
Access mode bit values
0
|
000
|
Single bit per clock
|
1
|
001
|
Single bit per clock (same as 0)
|
All additional modes (QSPI dual and quad modes) cannot be used,
as the management SoC only has pins for data lines 0 and 1.
The SPI flash can be accessed by bit banging when the enable is off.
To do this from the CPU, the entire routine to access the SPI flash
must be read into SRAM and executed from the SRAM.
Note
To sum up, the DDR enable, QSPI enable and CRM enable bits cannot be used due to the limited number of data pins.