Interrupts (IRQ) ?

The interrupt vector is set to memory address 0 (bottom of SRAM). The program counter switches to this location when an interrupt is received. To enable interrupts, it is necessary to copy an interrupt handler to memory location 0 . The PicoRV32 defines 32 IRQ channels, of which the Caravel chip uses only a handful, as described in the CPU IRQ channel definitions . All IRQ channels not in the CPU IRQ channel definitions always have value zero.

Table 18 CPU IRQ channel definitions ?

IRQ channel

description

4

UART interface data available

5

IRQ external pin ( IRQ E5 pin )

6

Housekeeping SPI IRQ

7

Assignable interrupt (see reg_irq7_source )

9

SPI controller data available, when enabled (see reg_spi_config )

10

Timer 0 expired, when enabled (see reg_timer0_config )

11

Timer 1 expired, when enabled (see reg_timer1_config )

The Caravel PicoRV32 implementation does not enable IRQ QREGS (see PicoRV32 description ).

The handling of interrupts is beyond the scope of this document (see RISC-V instruction set description ). All interrupts are masked and must be enabled in software.